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- Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
- 31st Design Automation Conference
- 1994

This paper presents a new method, based on Markov chain analysis, to evaluate the performance of schedules of behavioral specifications. The proposed performance measure is the expected number of clock cycles required by the schedule for a complete execution of the behavioral specification for any distribution of inputs. The measure considers both the… (More)

- Roman Kuznar, Franc Brglez, Baldomir Zajc
- 31st Design Automation Conference
- 1994

This paper considers the problem of partitioning a large logic circuit into a collection of subcircuits each of which is implemented with a device from a specific (FPGA) library. The objective function that we minimize is not only the total cost of devices to be used in the partition but also the size of the interconnect between the devices. We introduce… (More)

- Roman Kuznar, Franc Brglez, Krzysztof Kozminski
- 30th ACM/IEEE Design Automation Conference
- 1993

This paper considers the problem of obtaining a minimum-cost partitioning of a large logic circuit into a collection of subcircuits implementable with devices selected from a given library. Each device in the library may have a different price, size, and terminal capacity. We propose a multi-way partitioning algorithm based on a recursive application of the… (More)

- Ulf Schlichtmann, Franc Brglez, Michael Hermann
- DAC
- 1992

This paper introduces chamcteristic signatures for Boolean functions. The signatures do not ezhibit sensitivity to permutations of input vtrn”ables. We use these signatures to develop a method of rapidly matching subcircuits with cells in a (large) library. The procedure is analogous to hashing. This approach promises significant improvements for tibrary… (More)

- Roman Kuznar, Franc Brglez
- ICCAD
- 1995

In this paper, we introduce a new recursive partitioning paradigm PROP which combines (p)artitioning, (r)eplication, (o)ptimization, to be followed by another recursion of (p)artitioning, etc. We measure the quality of partitions in terms of total device cost, logic and terminal utilization, and critical path delay. Traditionally, the minimum lower bound… (More)

- Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory
- IEEE Transactions on Computer-Aided Design of…
- 1987

This paper presents ESPRIT, an automatic test pattern generation (ATPG) system for testing single stuck-at faults in combinational logic. ESPRIT generates test patterns by performing fault simulation on random patterns derived from nonuniformly distributed input signal probabilities. The system computes input signal probabilities that minimize a testability… (More)

The low-autocorrelation binary sequence (LABS) problem represents a major challenge to all search algorithms, with the evolutionary algorithms claiming the best results so far. However, the termination criteria for these types of stochastic algorithms are not well-defined and no claims have been made about optimality. Our approach to find the optima of the… (More)

- Matthias F. Stallmann, Franc Brglez, Debabrata Ghosh
- ALENEX
- 1999

The bigraph crossing problem, embedding the two vertex sets of a bipartite graph G = (V0; V1; E) along two parallel lines so that edge crossings are minimized, has application to circuit layout and graph drawing. We consider the case where both V0 and V1 can be permuted arbitrarily | both this and the case where the order of one vertex set is xed are… (More)

- Matthias F. Stallmann, Franc Brglez, Debabrata Ghosh
- ACM Journal of Experimental Algorithmics
- 2001

The bigraph crossing problem, embedding the two node sets of a bipartite graph along two parallel lines so that edge crossings are minimized, has applications to circuit layout and graph drawing. Experimental results for several previously known and two new heuristics suggest continued exploration of the problem, particularly sparse instances. We emphasize… (More)

- Justin E. Harlow, Franc Brglez
- International Journal on Software Tools for…
- 2001

Traditional approaches to the measurement of performance for CAD algorithms involve the use of sets of so-called “benchmark circuits.” In this paper, we demonstrate that current procedures do not produce results which accurately characterize the behavior of the algorithms under study. Indeed, we show that the apparent advances in algorithms which are… (More)