François Andrieu

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P. Batude, M. Vinet, B. Previtali, C. Tabone, C. Xu, J. Mazurier, O. Weber, F. Andrieu, L. Tosti, L.Brevard, B. Sklenard, P. Coudrain, S. Bobba, H. Ben Jamaa, P-E. Gaillardon, A. Pouydebasque, O. Thomas, C. Le Royer, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, L. Clavelier, G. De Micheli, S. Deleonibus, O. Faynot and T. Poiroux. CEAleti, Minatec Campus,(More)
This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal–oxide–semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were(More)
We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on(More)
We present TCAD simulations based on advanced mobility modeling including Surface Roughness (SR) and Remote Coulomb Scattering (RCS) effects, quantum correction and short channel effects. From these calibrated models, FDSOI 6T-SRAM cells are simulated and compared to experimental data. The very good agreement achieved between simulations and electrical data(More)
Thin film devices (FDSOI) are among the most promising candidates for next device generations due to their better immunity to short channel effects (SCE). In addition, the introduction of high-k and metal gate has greatly improved the MOSFETs performance by reducing the electrical oxide thickness (CET) and gate leakage current. However, if midgap metal gate(More)
Several types of floating-body capacitorless 1T-DRAM memory cells with planar SOI or multi-gate configuration are reviewed and compared. We show that 1T-DRAMs are also compatible with the ‘unified memory’ paradigm which aims at combining, within a single SOI transistor, volatile, nonvolatile and multiple-state memory functionalities. We focus on our(More)