François Andrieu

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3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance(More)
—This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage V T platform for digital circuits compatible with bulk complementary metal–oxide–semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were(More)
In this paper, we investigate the potential of strained Silicon-On-Insulator for the future advanced CMOS nodes. Strained FDSOI devices not only exhibit a 30% higher performance in term of I<sub>ON</sub>/I<sub>OFF</sub> but also show superior HC reliability at same drive current regardless of the back bias.