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A multiple input multiple output transceiver compliant with IEEE 802.11a/b/g and Japan wireless LAN standards is presented. The transceiver has two complete radio paths integrated on the same chip. When two chips are used in tandem to form a four path composite beam forming system, 15dB of link margin improvement is obtained. The transceiver was implemented(More)
—A field-programmable-gate-array (FPGA)-based built-in self-test (BIST) approach that is used for adaptive control in mixed-signal systems is presented. It provides the capability to perform accurate analog functional measurements of critical parameters such as the third-order intercept point, frequency amplitude and phase responses, and noise figure. The(More)
—We present a built-in self-test (BIST) approach based on a direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems. A main contribution of this paper is the BIST-based hardware implementation and measurement of amplifier linearity (IP3) and frequency response, including both phase and gain. The approach has(More)
—This paper describes a 9-bit 6.2-GHz low power quadrature direct digital synthesizer (DDS) implemented in a 0.18-m SiGe BiCMOS technology. With a 9-bit pipeline accu-mulator and two 8-bit sine-weighted current steering DACs, this DDS is capable of generating quadrature sinusoidal waveforms up to 3.15 GHz with a maximum clock frequency of 6.2 GHz. Packed(More)
—This paper presents a 12 GHz direct digital synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 m SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of(More)
—A 12-bit Vernier ring time-to-digital converter (TDC) with time resolution of 8 ps for digital-phase-locked-loops (DPLL) is presented. This novel Vernier ring TDC places the Vernier delay cells and arbiters in a ring format and reuses them for the measurement of the input time interval. The proposed TDC thus achieves large detectable range, fine time(More)
We present a single-chip tuner RFIC for the newly established Chinese Mobile Multimedia Broadcasting (CMMB) standard. This mobile digital TV tuner covers the CMMB frequencies from 2.635GHz to 2.660GHz. Implemented in a 0.35um SiGe technology with 4mm 2 die size, this tuner IC achieves noise figure of 2dB, input sensitivity of-100dBm, IIP3 of 17dBm, and(More)
—This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF–dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in(More)