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—This paper presents a rigorous analytical model for analyzing the effects of local oscillator output imperfections such as phase/amplitude imbalances and phase noise on M-ary quadrature amplitude modulation (M-QAM) transceiver performance. A closed-form expression of the error vector magnitude (EVM) and an analytic expression of the symbol error rate (SER)(More)
—A field-programmable-gate-array (FPGA)-based built-in self-test (BIST) approach that is used for adaptive control in mixed-signal systems is presented. It provides the capability to perform accurate analog functional measurements of critical parameters such as the third-order intercept point, frequency amplitude and phase responses, and noise figure. The(More)
We present a Built-In Self-Test (BIST) approach based on direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems. Of particular interest, and a main contribution of this paper, is the BIST-based hardware implementation and measurement of amplifier linearity (IP3) test using DDS. The approach described in this(More)
—We present a built-in self-test (BIST) approach based on a direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems. A main contribution of this paper is the BIST-based hardware implementation and measurement of amplifier linearity (IP3) and frequency response, including both phase and gain. The approach has(More)
—This paper presents a 2GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Nonlinear current steering digital to analog converter (DAC) has been utilized to convert phase word to sine wave amplitude directly without area consuming Rom for sine look-up table, which is the speed bottleneck of the DDFS circuit. In order to achieve high speed(More)
This paper presents a 0.6V quadrature voltage-controlled oscillator (QVCO) with a novel capacitive coupling technique, which is employed not only for quadrature signal coupling, but also for noise reduction. As a result, the proposed QVCO can even achieve 3 to 5dB lower phase noise than a single-phase VCO of the same kind. Optimized capacitive coupling(More)
—A 12-bit Vernier ring time-to-digital converter (TDC) with time resolution of 8 ps for digital-phase-locked-loops (DPLL) is presented. This novel Vernier ring TDC places the Vernier delay cells and arbiters in a ring format and reuses them for the measurement of the input time interval. The proposed TDC thus achieves large detectable range, fine time(More)