Florin Balasa

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This paper addresses the problem of device-level placement for analog layout, focusing mainly on symmetry-related aspects. Different from most of the existent analog placement approaches, employing basically simulated annealing optimization algorithms operating on flat (absolute) spatial representations [4], our model uses a more recent topological(More)
The traditional way of approaching placement problems in computer-aided design (CAD) tools for analog layout is to explore an extremely large search space of feasible or unfeasible placement configurations, where the cells are moved in the chip plane (being even allowed to overlap in possibly illegal ways) by a stochastic optimizer. This paper presents a(More)
The ordered tree (O-tree) representation has recently gained much interest in layout design automation. Different from previous topological representations of non-slicing floorplans, the O-tree representation is simpler, needs linear computation effort to generate a corresponding layout, and exhibits a smaller upper-bound of possible configurations. This(More)
This paper presents an improved topological algorithm for device-level analog placement with symmetry constraints. Based on the exploration of symmetric-feasible sequence-pairs [1], the technique employs an efficient model of priority queue [3]. The use of this data structure entails a complexity of O(G·n log logn) for each code evaluation, where n and G(More)
The traditional way of approaching devicelevel placement problems for analog layout is to explore a huge search space of absolute placement representations, where cells are allowed to illegally overlap during their moves [2, 7, 8]. This paper presents a novel analog placement technique operating on the set of binary tree representations of the layout [3],(More)
size and power in video and image processing systems L.Nachtergaele, F.Catthoor, F.Balasa, F.Franssen, E.De Greef, H.Samsom, H.De Many IMEC, Kapeldreef 75, B3001 Leuven, Belgium yProfessor at the Katholieke Universiteit Leuven, Belgium Abstract Video and image processing applications deal with large amounts of data which have to be stored and transferred.(More)
Memory cost is typically responsible for up to 80% of the chip andlor board area of most video and imuge processing system realisations. In this paperj we present a novel technique founded on data-jlow analysis which allows to address the problem of background menxny size evaluation for a given non-procedural algorithm speci$cation. Usually, the number of(More)
In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. Moreover, the area cost is often largely dominated by the memory modules. The computation of the memory size is an important step in the process of designing an optimized (for area and/or power) memory architecture for(More)