Florentine Dubois

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In this paper, we propose a distributed routing algorithm for vertically partially connected regular 2D topologies of different shapes and sizes (e.g., 2D mesh, torus, ring). The topologies that are the target of this algorithm are of practical interest in the 3D integration of heterogeneous dies using ThroughSilicon-Vias (TSVs). Indeed, TSV-based 3D(More)
In this paper, we detail the design and implementation of a router for vertically-partially-connected 3D-NoCs based on stacked 2D-meshes. This router implements the necessary hardware to support a recently introduced routing algorithm called "Elevator-First", which targets topologies with irregularly placed vertical connections in a deadlock free manner,(More)
Networks-on-chips (NoCs) have emerged as an effective interconnection solution for modern MPSoCs. However, NoCs are characterized by a wide range of parameters and early performance estimations have become keys. We propose an approach to build static cost models (e.g. area) of NoC components. The modeling relies on Kriging theory, which catches the complex(More)
In the last decade, Networks-on-chip (NoCs) have emerged as an efficient and flexible interconnect solution to handle the increasing number of processing elements included in Systems-on-chip (SoCs). NoCs are able to handle high-bandwidth and scalability needs under tight performance constraints. However, they are usually characterized by a large number of(More)
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