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Procedure placement using temporal-ordering information: dealing with code size expansion
TLDR
In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Expand
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On the Complexity of Register Coalescing
TLDR
This paper is devoted to the complexity of the coalescing phase, in particular in the light of recent developments on the SSA form. We distinguish several optimizations that occur in coalescing heuristics: a) aggressive coalescing moves aggressively, regardless of the colorability of the resulting interference graph; b) conservative coalescing removes as many moves as possible while keeping the colorable of the graph; c) incremental conservative coaleszing removes one particular move while keepingThe graph colorable. Expand
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On the complexity of spill everywhere under SSA form
TLDR
Compilation for embedded processors can be either aggressive (time consuming cross-compilation) or just in time (embedded and usually dynamic). Expand
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Étude des problèmes de spilling et coalescing liés à l'allocation de registres en tant que deux phases distinctes. (A Study of Spilling and Coalescing in Register Allocation as Two Separate Phases)
TLDR
The goal of register allocation is to assign the variables of a program to the registers or to spill them to memory whenever there are no register left. Expand
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Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How
TLDR
This work was supported by a contract with STMicroelectronics, Grenoble, France. Expand
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Register allocation and spill complexity under SSA
TLDR
This report deals with the problem of choosing which variables to spill during the register allocation phase, which is a highly studied problem for compiler design, but nevertheless NP-complete. Expand
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Advanced conservative and optimistic register coalescing
TLDR
In the context of embedded systems, it is crucial to minimize memory transfers to reduce latency and power consumption. Expand
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Parallel copy motion
TLDR
This paper presents parallel copy motion, a technique for optimizing register-allocated codes, which amounts to moving a group of parallel copy instructions from a program point to another.Recent results on the static single assignment (SSA) form open promising directions for the design of register allocation heuristics for just-in-time compilation. Expand
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Register Allocation: What does Chaitin's NP-completeness Proof Really Prove?
Register allocation is one of the most studied problem in compilation. It is consideredas an NP-complete problem since Chaitin, in 1981, showed that assigning temporary variablesto k machineExpand
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D 5 . 5 – BOAST : a Metaprogramming Framework to Produce Portable and Efficient Computing Kernels for HPC Applications Version 1 . 0
Contract Number 610402 Project Website www.montblanc-project.eu Contractual Deadline M18 Dissemintation Level PU Nature Report Coordinator CNRS Contributors Florent Bouchez Tichadou (UJF), ThierryExpand
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