Florence Azaïs

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The paper proposes a BIST approach for deriving the main characterization parameters of ADCs from histogram data. An adequate choice of input stimulus and time decomposition scheme is proposed in order to minimize the extra on-chip hardware required to extract these parameters. The idea of time decomposition consists in replacing classical(More)
This paper validates a linear histogram BIST scheme for ADC testing. This scheme uses a time decomposition technique in order to minimize the required hardware circuitry. A practical implementation is described and the structure together with the operating mode of the different modules are detailed. Through this practical implementation, the performances(More)
60 0740-7475/03/$17.00 © 2003 IEEE Published by the IEEE Computer Society IEEE Design & Test of Computers DEVELOPMENTS IN circuit design and process technology have enabled designers to implement effective mixed-signal ICs, in which complex digital blocks are integrated along with analog circuitry on a single chip. Testing such ICs, however, is the major(More)
Testing of Analog-to-Digital Converters is classically composed of two successive and independent phases: the histogram-based test technique evaluating static specifications and the spectral analysis technique evaluating the dynamic performances. Consequently, the fundamental objective here is to investigate the feasibility of an alternative test flow(More)