Flávio Rech Wagner

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A software design method is presented, based on a virtual finite state machine (VFSM) concept. The concept defines a virtual environment that allows the finite state machine to be an entirely table driven software module. A hybrid finite state model is used to achieve a superior design clarity. The method separates the control part of the design problem(More)
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously proposed technique for the reuse of an on-chip network is extended to consider power consumption during test, while minimizing the system testing time. Experimental results with the(More)
This work presents a proposal to use aspect orientation in the analysis and design of distributed embedded real-time systems (DERTS). These systems have several requirements directly related to their main characteristics, the so-called non-functional requirements (NFR), which refer to orthogonal properties, conditions, and restrictions that are spread out(More)
Networks-on-chip (NoCs) are communication architecture alternatives for complex Systems-on-Chip (SoCs) designs, due to their high scalability and bandwidth. In this paper, we consider a heterogeneous NoC as an alternative to match performance and energy requirements for dedicated applications. By employing an optimized mix of different routers, a(More)
This paper presents the system synthesis techniques available in SES, a CAD environment for the specification, simulation, and synthesis of embedded electronic systems that can be modeled as a combination of analog parts, digital hardware, and software. SES is based on a distributed, object-oriented system model, where objects are initially modeled by their(More)
High-level performance estimation of embedded software implemented in a particular processor is essential for a fast design space exploration, when the designer needs to evaluate different processor architectures (and their different versions) and also different task allocations in a multiprocessor system. The development of fast and adequate performance(More)
The partitioning of applications into hardware and software is an important issue in embedded systems, opening room for high level specifications as well as the exploration of different implementation strategies. This paper presents a software architecture to specify threads in hardware in the context of the real time specification for Java (RTSJ) standard.(More)
This work analyzes, the mapping of applications onto generic regular Networks-on-Chip (NoCs). Cores must be placed considering communication requirements so as to minimize the overall application execution time and energy consumption. We expand previous mapping strategies by taking into consideration the dynamic behavior of the target application and thus(More)
This work discusses the adaptation of routers characteristics in Networks-on-Chip to QoS-dependent application requirements, in particular with respect to the fulfillment of task deadlines. The utilization of a flow control mechanism for input buffers with increasing priority for blocked messages and dropping of old packets allows a reduction in the number(More)