Fernando Pescador

Learn More
In this paper, the implementation of a digital signal processor (DSP) based H.264 decoder for a multi-format set-top box is described. Baseline and main profiles are supported. Using several software optimization techniques, the decoder has been fitted into a low-cost DSP. The decoder alone has been tested in simulation, achieving real-time performance with(More)
This paper provides a concrete implementation and comprehensive assessment of the energy-based fair queuing (EFQ) scheduling algorithm based on the Linux operating system. EFQ is an extended application of the classical fair queuing algorithm in the energy domain. It is designed to provide proportional power sharing as well as effective time-constraint(More)
Latest generation DSPs are becoming more efficient, being able to improve their forerunners while reducing their internal memory size to lower the cost. In this paper, an H.264 video decoder based on a latest generation DSP is described. Both the EDMA and the memory architecture of the processor have been fully exploited to increase the execution speed.(More)
High Efficiency Video Coding (HEVC) is a new video coding standard created by the JCT-VC group within ISO/IEC and ITU-T. HEVC is targeted to provide the same quality as H.264 at about half of the bit-rate and will replace soon to its predecessor in multimedia consumer applications. Up to now, only a few decoder implementations have been reported, most of(More)
Currently, the usefulness of many mobile systems is largely limited by the battery lifetime. In this paper, energy-based fair queuing (EFQ) is proposed as a pivotal instrument to maximize the user experience in this type of system. Energy-based fair queuing is a novel class of energy-aware scheduling algorithms that support proportional energy use,(More)
The new High Efficiency Video Codec (HEVC) standard will replace H.264 soon in consumer multimedia applications. The open source project OpenHEVC is working on an efficient implementation of the HEVC decoder in C language. In this paper, an HEVC decoder based on OpenHEVC for DSP technology is presented. The tests show that it outperforms by 2.3 a previously(More)
In this paper, an H.264 video decoder based on the new TMS320DM6437 (DaVinci) DSP is described. In this work both, DMA and memory architecture of the processor are fully exploited to improve the decoder performance. Profiling tests have been carried out in simulation using digital TV streams and DVD transcoded sequences. Performance is 10% better than that(More)
In this paper, the implementation of a Main Profile H.264 decoder based on a DM642 digital signal processor is described. An initial standard compliant raw-C decoder has been optimized in speed for the target processor. The parallelism between algorithm execution and data movement has been fully exploited using DMA. Also, critical parts of the algorithm(More)
In this paper, the implementation of a baseline profile H.264 decoder based on a DM 642 digital signal processor is described. An initial standard compliant raw-C decoder has been optimized in speed for the target processor. The parallelism between algorithm execution and data movement has been fully exploited using DMA. Also, critical parts of the(More)
In this paper, an implementation of the energy-based fair queuing (EFQ) scheduling algorithm based on Linux is presented. EFQ is an extended application of the fair queuing algorithm in the domain of energy management for achieving proportional energy use among user applications. The Linux scheduling structure has been effectively utilized to ease the EFQ(More)