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Using data for 25,780 species categorized on the International Union for Conservation of Nature Red List, we present an assessment of the status of the world's vertebrates. One-fifth of species are classified as Threatened, and we show that this figure is increasing: On average, 52 species of mammals, birds, and amphibians move one category closer to(More)
Phase Change Memory (PCM) is currently postulated as the best alternative for replacing Dynamic Random Access Memory (DRAM) as the technology used for implementing main memories, thanks to its significant advantages such as good scalability and low leakage. However, PCM also presents some drawbacks compared to DRAM, like its lower endurance. This work(More)
In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power consumption, we propose in this paper a straightforward filtering technique. The mechanism is based on a highly accurate forwarding predictor that determines if a load instruction(More)
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with off-chip memory accesses. One of the main challenges of buffering a large number of instructions, however, is the implementation of a scalable and efficient mechanism to detect memory(More)
The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient(More)
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-order execution of memory instructions. Traditional CAM-based associative queues can be very slow and energy hungry. In this paper we introduce two new management schemes. The first(More)
Modern microprocessors incorporate sophisticated techniques to allow early execution of loads without compromising program cor-rectness. To do so, the structures that hold the memory instructions (Load and Store Queues) implement several complex mechanisms to dynamically resolve the memory-based dependences. Our main objective in this paper is to design an(More)