Fernanda Gusmão de Lima Kastensmidt

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Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can(More)
A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by(More)
552 0740-7475/04/$20.00 © 2004 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers ICS ARE SENSITIVE to upsets that occur in aerospace. More recently, ICs have also become sensitive to upsets at ground level because of the continual evolution of fabrication technology for semiconductors. Drastic device shrinkage, power supply(More)
Network-on-chip (NoC) designs are based on a compromise among latency, power dissipation, or energy, and the balance is usually defined at design time. However, setting all parameters, such as buffer size, at design time can cause either excessive power dissipation (originated by router under utilization), or a higher latency. The situation worsens whenever(More)
50 0740-7475/05/$20.00 © 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers THE TECHNOLOGICAL EVOLUTION of the IC fabrication process, consisting of device shrinking, power supply reduction, and increasing operating speeds, has significantly reduced the manufacturing yield and reliability of very deep-submicron (VDSM) ICs(More)
A Network-on-Chip with large FIFO size ensures performance during the execution of different traffic flow, but unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers to reach higher throughput incurs in extra dissipation for the mean case, which is much more frequent. In(More)