Fernand Boéri

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In order to reduce the cost, the time-to-market and to make the most pertinent choices, it becomes essential to allow designers to evaluate, very soon in the design phase, a given application performances with respect to the targetted architecture. So, we have decided to build a modelling and simulation environnement in order to evaluate digital hardware(More)
This paper presents a new synthesis approach for dedicated systems. The aim of our synthesis scheme is to achieve an automatic exploration of VLIW processor architectures from a pure C description of the input system. The innovation consists in the fact that unit allocation must manage the fact that a function may be realized either by dedicated functional(More)
The major purpose of this paper is to present the partitioninglschedulinglallocation algorithm developed for the CAPSYS method. The aim of this project is to define a tool able to automatically design dedicated and embedded VLIW architectures for large and complex applications. It inherits a sizeable knowledge-pool from the wider field of parallel(More)
The very high integration rate and the increasing complexity of digital hardware architectures and embedded applications lead designers to search for new tools and methods. In order to reduce the time-to-market it becomes essential to allow designers to evaluate performances of a given application with the targetted architecture very soon in the design(More)
Know-how is the most useful mean for designing new processors before a complete hardware description. The integration rate is increasing very quickly and the time-to-market has to be dramatically reduced because of the rapid evolution of technology. Therefore, reuse and rapid-prototyping are definitely a major issue to integrate existing architectures and(More)