Feng-Wei Kuo

Learn More
Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball(More)
We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also(More)
We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s) discrete-time (DT) architecture with intermediate frequency (IF) placed beyond the 1/f noise corner of MOS devices. New multistage multi-rate charge-sharing bandpass filters are adapted to achieve(More)
We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F<sub>2</sub> digital power(More)
We propose a new architecture of an all-digital PLL (ADPLL) for advanced cellular radios that is optimized for 28 nm CMOS. It is based on a wide tuning range, fine-resolution class-F DCO with only switchable metal capacitors and a phase-predictive TDC. The 8mW DCO emits -157 dBc/Hz at 20MHz offset at ~2 GHz, while fully satisfying metal density rules. The(More)
A 3D IC heterogeneous chip integration of 65nm RF receiver, 28nm baseband processor, and 40nm DRAM on a proprietary CoWoS structure is demonstrated and its electrical characterization of KGS (Known Good Stack) has revealed a highly comparable system performance as compared to that of the KGD (Known Good Die) testing data. Moreover, an innovative system BIST(More)
Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art quality factor (Q) = 64 in 2.4GHz inductor has been demonstrated for RF systems. For the first time, radio frequency (RF) circuits with InFO-WLP have been fabricated to illustrate how the high Q inductor can be used to dramatically improve performance and power consumption(More)
An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of -53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO,(More)
Ball mount technology uses performed solder spheres dropping through a metal template onto wafer at once. This technology is directly producing bumps on wafer with high throughput and consistent bump results. Ball mounting process without using electroplating decreases cost and chemical pollution. This technique is applicable for many applications but(More)
We propose a new approach to an on-chip clock distribution scheme. It is based on distributed multi-GHz LC-tank oscillators generating local clocks. The oscillators are mutually coupled to align their frequencies and are further subharmonically injection-locked to a much lower frequency reference to align their phases. The final phase calibration is via(More)