Felix Tarköy

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0163-6804/99/$10.00 © 1999 IEEE dvanced error correcting codes and/or coded modulation schemes are an essential part of most modern data transmission systems for both wireless and copper wire applications. As shown in Fig. 1, the coding system consists of two parts: an encoder in the transmitter and a decoder in the receiver. The channel in Fig. 1 comprises(More)
An all-analog high-speed decoding technique is described which is suitable for magnetic recording (MR) and other computationally demanding applications. A decoder for a binary (18,9,5) tail-biting trellis code, which is much simpler than the codes used for MR, has been chosen to demonstrate this technique. It achieves a decoding rate of 100 Mbit/s at a(More)
The design of various high-speed interface architectures for off-chip connections to and from analog, iterative VLSI decoders is discussed. It is shown that for applications with high transmission rates and low to medium accuracy, MOSFET-only R-2R ladders in combination with switched-current memory cells are ideally suited, due to their current mode nature(More)
The sum-product algorithm (probability propagation) can be mapped directly into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes. Patent application pending. This research was supported by the Swiss National Science Foundation under Grant(More)
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