Felix Ng

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We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynamic power dissipation during scan testing in registers and combinational cells can be significantly reduced without modifying the clock tree of the design. The proposed architecture(More)
With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are <b>hitting capacity and performance</b> bottlenecks. Currently, hierarchical synthesis flows for large designs lack complete designfor-test (DFT) support. With this paper, we address a solution, involving the introduction of test(More)
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