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A multi-model power estimation engine for accuracy optimization
TLDR
This paper describes a new multi-model power estimation engine that selects the macromodeling technique leading to the least estimation error for a given system component depending on the properties of its input-vector stream. Expand
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Versatile system-level memory-aware platform description approach for embedded MPSoCs
TLDR
In this paper we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. Expand
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A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization
TLDR
This paper describes two different approaches for a new multi-model power estimation engine. Expand
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SystemC-Based Power Evaluation with PowerSC
TLDR
We present PowerSC, a power estimation framework which instruments SystemC for power characterization, modeling and estimation. Expand
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Characterizing the Energy Consumption of Software Transactional Memory
TLDR
The well-known drawbacks imposed by lock-based synchronization have forced researchers to devise new alternatives for concurrent execution, of which transactional memory is a promising one. Expand
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On the energy-efficiency of software transactional memory
TLDR
We provide, in this paper, a comprehensive energy analysis of a standard STM design and propose novel scratchpad-based energy-awareSTM design strategies. Expand
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Empirical Web server power modeling and characterization
TLDR
This paper presents a new approach for power models for Web servers, based on ranges of CPU usage values and performance server statistics. Expand
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Fast instruction set customization
TLDR
We describe an automatic methodology to select the custom instructions from the given application code, in a way that there is no need of compensation code or other modifications in the application. Expand
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STM versus lock-based systems: An energy consumption perspective
TLDR
We present a comprehensive study on the energy consumption of a state-of-the-art STM (Software Transactional Memory) implementation using STAMP, a representative set of transactional workloads, comparing it to its lock-based counterpart. Expand
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On the Limitations of Power Macromodeling Techniques
TLDR
This paper discusses the limitations of macromodeling techniques that can lead to unacceptably high estimation errors. Expand
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