Felice Crupi

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A voltage reference circuit operating with all transistors biased in weak inversion, providing a mean reference voltage of 257.5 mV, has been fabricated in 0.18 m CMOS technology. The reference voltage can be approximated by the difference of transistor threshold voltages at room temperature. Accurate subthreshold design allows the circuit to work at room(More)
In this paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the first time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with a high/metal gate stack, as well as on 45-nm Si pMOSFETs with identical gate stack for comparison. In the reference SiGe(More)
Channel hot carrier (CHC) stress is observed to result in higher variability of degradation in deeplyscaled nFinFETs than bias temperature instability (BTI) stress. Potential sources of this increased variation are discussed and the intrinsic time-dependent variability component is extracted using a novel methodology based on matched pairs. It is concluded(More)
The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavior of nand p-channel MOSFETs with high-κ gate dielectrics and metal gates is investigated. Decreasing the interfacial layer thickness from 0.8 to 0.4 nm affects the 1/f noise in two ways. 1) The mobility fluctuations mechanism becomes the main source of 1/f noise(More)
Ultralow noise measurements often require the application of signal processing and correction techniques to go beyond the noise performances of front-end amplifiers. In this paper, a new method for the voltage noise measurement is proposed, which allows, at least in principle, the complete elimination of the noise introduced by the amplifiers used for the(More)
This study aims to understand the potential of bulk FinFET technology from the perspective of suband nearthreshold logic circuits down to 100-mV bias voltage. Measurements are performed on bulk FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and with a high-k/metal-gate stack having an equivalent thickness in(More)
The introduction of SiGe channel pMOSFETs for high mobility devices is expected to enhance the impact ionization phenomenon, making it necessary to study Hot Carrier (HC) degradation also for the p-channel MOSFET reliability. The study of pure HC effects on pMOSFETs is complicated due to the mixing with Negative Bias Temperature Instability (NBTI). In the(More)