Federico A. Altolaguirre

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— A new silicon controlled rectifier-based power-rail electrostatic discharge (ESD) clamp circuit was proposed with a novel trigger circuit that has very low leakage current in a small layout area for implementation. This circuit was successfully verified in a 40-nm CMOS process by using only low-voltage devices. The novel trigger circuit uses a(More)
—A new power-rail ESD clamp circuit is proposed and verified with consideration of the gate leakage issue in 65-nm CMOS technology. The proposed circuit can reduce the total leakage current of the traditional power-rail ESD clamp circuit in two orders of magnitude. Moreover, the proposed circuit reduces the required silicon area by boosting the capacitor(More)
— This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully(More)
— SCR is the preferred ESD protection device in nanoscale CMOS technologies due to the better area efficiency compared the BIGFET, virtually no leakage current and smaller capacitance. The main drawback of the SCR is the slow turn-on speed, which is solved by adding dummy gates to block the STI formations inside the SCR structure. This work demonstrates(More)
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