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A novel processor architecture for hardware execution of Java bytecodes is presented. Stack dependency is resolved by the use of a hardware bytecode folding algorithm coupled with Tomasulo's scheduling algorithm. In this paper, we present a framework for adapting Tomasulo's algorithm for bytecode folding based Java processors. We discuss a set of(More)
In this paper, an efficient (in the AT and AT2 senses) systolic implementation of state-space realization of the IIR digital filters is presented. The technique used is based on block-state description in which the state update matrix is full. The new implementation has significantly reduced number of processor elements while simultaneously maintaining a(More)