Farshad Safaei

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Parallel computers, such as multiprocessors system-on-chip (Mp-SoCs), multicomputers and cluster computers, are consisting of hundreds or thousands multiple processing units and components (such as routers, channels and connectors) connected via some interconnection network that collectively may undergo high failure rates. Therefore, these systems are(More)
Multi-stage interconnection networks (MINs) have frequently been proposed as connection means in traditional parallel systems and networks-on-chip. Most of the existing papers consider some specific traffic patterns over these networks, such as uniform traffic. In this paper, the performance of MIN operating under different types of traffic patterns is(More)
In modern world, all sciences especially engineering have insatiable demand for more power of processing. Although the use of modern micro-architectures has increased the performance of processors, this increment is only part of speeding up in responding such these demands. In fact, the need of some applications to parallel systems in large scales makes(More)
Several analytical models have recently been proposed for circuit-switched interconnect networks under the uniform traffic pattern. However, there has been hardly any model reported yet that deals with other important non-uniform traffic patterns, such as hot-spots. This paper presents a new mathematical model to capture the mean message latency in the(More)
Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged. Employing wireless communication links between(More)