Farhat Thabet

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In order to optimize global energy efficiency in the context of dynamic process, voltage and temperature variations in advanced nodes, a fine-grain adaptive voltage and frequency scaling architecture is proposed for multiprocessor systems-on-chip (MPSoC), where each processing element is an independent voltage-frequency island. This architecture has been(More)
The current trend in embedded computing consists in increasing the number of processing resources on a chip. Following this paradigm, cluster-based many-core accelerators with a shared hierarchical memory have emerged. Handling synchronizations on these architectures is critical since parallel implementations speed-ups of embedded applications strongly(More)
The current trend in embedded computing consists in increasing the number of processing resources on a chip. Following this paradigm, the STMicroelectronics/CEA Platform 2012 (P2012) project designed an area- and power-efficient many-core accelerator as an answer to the needs of computing power of next-generation data-intensive embedded applications.(More)
In order to optimize global energy efficiency in the context of dynamic Process-Voltage-Temperature variations in advanced nodes, a fine-grain Adaptive Voltage and Frequency Scaling architecture is proposed and implemented on a 32 nm GALS Multi-Processor SoC. Each Processing Element is an independent Voltage-Frequency island and shows up to 18.2% energy(More)
The design of complex Digital Signal Processing (DSP) hardware accelerators implies to minimize architectural cost and to maximize timing performances. Exploring different communication architectures and timing behaviors is thus a key step in the modern system design flows. In this paper, we present a methodology that permits the design space exploration of(More)
The increasing design complexity of manycore architectures at the hardware (HW) and software (SW) levels imposes to have powerful tools capable of validating every functional and non-functional property of the architecture. At the design phase, the chip architect needs to explore several parameters from the design space, and iterate on different instances(More)
Exploring different communication architectures and timing behaviors is a key step in modern system design flows. This paper describes a behavioral description model (BDM) that allows design space exploration of DSP applications at different abstraction levels. The proposed approach consists in embedding a sequential function into a BDM object that includes(More)
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