Farhana Rashid

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In recent years, circuit size has increased due to scaling down of technology. Controlling power dissipation in these large circuits during test sessions is one of the major concerns in VLSI testing. In general power dissipation of a system in test mode is higher than the normal mode. This extra power can cause problems such as instantaneous power surge(More)
Weighted random patterns (WRP) and transition density patterns (TDP) can be effectively deployed to optimize test length with higher fault coverage in scan-BIST circuits. New test pattern generators (TPG) are proposed to generate weighted random patterns and controlled transition density patterns to facilitate efficient scan-BIST implementations. We achieve(More)
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