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This paper presents a simulation-based hierarchical sizing and biasing tool for analog integrated circuits design. The tool allows the designer to express the sizing procedure in terms of sizing and biasing operators. These operators are technology independent, hence the documented procedure can be easily ran over different technologies. A procedure has(More)
—This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The(More)
This paper presents an algorithm, based on the fixed point iteration, to solve for sizes and biases using transistor compact models such as BSIM3v3, BSIM4, PSP and EKV. The proposed algorithm simplifies the implementation of sizing and biasing operators. Sizing and biasing operators were originally proposed in the hierarchical sizing and biasing(More)
In this paper, a new method for developing smart parameterized generators for analogue devices is presented. A device is an atomic analogue cell that performs an elementary and standard function such as the differential pair and the current mirror. A device is smart since it can be electrically and physically adapted. In the proposed method, the device(More)
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