Fangpo He

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Cache access latency and efficient usage of on-chip capacity are critical factors that affect the performance of the chip multiprocessor (CMP) architecture. In this paper, we propose a SPS2 cache architecture and cache coherence protocol for snooping-based CMP, in which each processor has both private and shared L2 cache to balance latency and capacity. Our(More)
The Chip Multiprocessor (CMP) architecture offers parallel multi-thread execution and fast retrieval of shared data that is cached on-chip. In order to obtain the best possible performance with the CMP architecture, the cache architecture must be optimised to reduce time lost during remote cache and off-chip memory accesses. Many researchers proposed CMP(More)
This paper presents a new algorithm for modelling the behaviour of dynamic video. The PDP (Projected Difference Pattern) is designed to perform simple spatiotemporal processing with a strong focus on efficiency of real-time implementation. In its simplest implementation, the algorithm is shown to be suitable for generating dynamic background models, motion(More)