Learn More
Network-on-Chip (NoC) has been proposed as a new solution to deal with the global communication problem of complex System-on-Chip (SoC), which faces huge design challenges. A performance evaluation tool is essential for designers to explore the design space, verify functionality and estimate performance of designs. This paper presents a performance(More)
Vision-based unstructured road following is a challenging task due to the nature of the scene. This paper describes a novel algorithm to improve the accuracy and robustness of vanishing point estimation with very low computational cost. The novelties of this paper are three aspects: 1) We use joint activities of four Gabor filters and confidence measure for(More)
—Fast and accurate full-system simulation is needed for MPSoC design space exploration to achieve tight time-to-market design goals. In the field of full-system simulation , transaction level modeling with SystemC and traditional instruction set simulators (e.g. M5) based on C/C++ have their own advantages, separately. In this paper, a novel method for(More)
In this paper, a SMC based mobile robot controller is designed, which can achieve chatter alleviation, matched and mismatched disturbances regulation and stability at the same time. Specifically, there are four main contributions in this paper. First, new hierarchical sliding surfaces are designed in the paper for mobile robot subject to matched and(More)
With the rapid increase in the number of processor cores integrated on Network-on-Chips (NoCs) and higher requirements for system reliability, fault tolerance is becoming a great challenge in the design process. In this paper, a fast two-step topology reconfiguration (FTTR) algorithm is proposed to solve the reconfiguration mapping problem in NoCs for(More)