Learn More
A small-granularity solution with high performance and low area cost for fault-tolerant routing of hard error in 2D-Mesh Network-on-Chip is proposed. This solution presents a new fault model, defines separately node-fault and link-fault, reduces situations classified as node-fault effectively, and consequently improves the performance of the network. By(More)
Most streaming applications, such as multimedia and digital signal processing (DSP) application, are iterative in nature, so pipelined implementation can be introduced into streaming application for high throughput. In this case, as a communication-centric design approach, NoC is capable of solving communication bottleneck incurred by throughput increment.(More)
A novel architecture is proposed to tolerate faulty cores in NoC-based MPSoCs. By dynamical reconfiguration of router/core connections, network can achieve complete restoration after faults and then former system states can resume without performance degradation. Moreover, a reconfiguration scheme is proposed to optimize system's recovery efficiency. By(More)
A novel reconfigurable 2D mesh Network-on-Chip (NoC) architecture (REmesh) and a topology reconfiguration algorithm (TRARE) are proposed in this paper. Compared with a conventional 2D mesh, REmesh, which employs a few more routers and multiplexers, can be easily reconfigured to restore a 2D mesh topology to tolerant core faults in NoCs. Based on REmesh,(More)
Network on Chip (NoC) is an approach to designing the communication subsystem between IP cores in a System on a Chip (SoC). NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs. The purpose of NOC is to solve the choke point in communication and the clock problem from architecture. Each route in NOC(More)
  • 1