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—In this paper we propose and implement a methodology for power reduction in digital circuits, closing the gap between conceptual (by designer) and local (by EDA) clock gating. We introduce a new class of coarse grained local clock gating conditions and develop a method for detecting such conditions and formally proving their correctness. The detection of(More)
We present a power optimization methodology that provides a fast and accurate power model for programmable architectures. The approach is based on a new tool that estimates power consumption from a register transfer level (RTL) module description, activity files and technology library. It efficiently provides an instruction-level accurate power model and(More)
Thèse dirigée par Oded Maler et codirigée par Fahim Rahim préparée au sein Verimag et de EDMSTII Acknowledgement The years I spent in Grenoble working on this thesis were enriching both professionally and personally. I would like to thank my supervisor Oded Maler for his guidance and support. He was always there to provide counsel and always found time for(More)
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