Fahad M. Alzahrani

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ECC for Ultra-Large, Single-Chip Memory Systems Fahad Alzahrani Tom Chen Department of Electrical Engineering Colorado State University Fort Collins, CO 80523 2 The Existing ECC Codes Soft errors resulted from alpha-particle strikes are one of the major actors that reduces the reliability of memory chip is to employ an on-chip error-correcting code (ECC).(More)
We present a high performance edge detection architecture for real-time image processing applications. The architecture is nely pipelined. The proposed ASIC is capable of producing one edge{pixel every clock cycle. At a clock rate of 10 MHz, the architecture can process 30 frames per second, where the size of each frame is 640 480 8{bit pixels. The ASIC was(More)
Computer manipulation of images is generally defined as Digital Image Processing (DIP). DIP is employed in variety of applications, including video surveillance, target recognition, and image enhancement. Some of the algorithms used in image processing include convolution, edge detection and contrast enhancement. These are usually implemented in software(More)
In this paper, we present a stand alone ASIC architecture for a new edge detection algorithm, which applies the absolute diierence mask (ADM). The ASIC is built of three major blocks: smoothing, edge strength, and detection and localization blocks. To allow high{ speed processing, the architecture is nely pipelined. The proposed ASIC is capable of producing(More)
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