Fahad M. Alzahrani

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We present a high performance e dge detection architecture for real-time image processing applications. The architecture is nely pipelined. The proposed A-SIC is capable of producing one edgeepixel every clock cycle. At a clock rate of 10 MHz, the architecture c an process 30 frames per second, where the size of each frame is 640480 88bit pixels. The ASIC(More)
OBJECTIVES To investigate the tensile strength of repaired flexor profundus tendons in young lambs, which would be equivalent to repairs in children older than 2 years of age. METHODS A comparative in-vitro experimental study conducted at King Saud University, Riyadh, Kingdom of Saudi Arabia from October 2014 to December 2015. We utilized 30 flexor(More)
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