• Publications
  • Influence
A Survey and Evaluation of FPGA High-Level Synthesis Tools
  • R. Nane, V. Sima, +9 authors K. Bertels
  • Engineering, Computer Science
  • IEEE Transactions on Computer-Aided Design of…
  • 1 October 2016
TLDR
High-level synthesis (HLS) is increasingly popular for the design of high performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. Expand
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  • 22
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Bambu: A modular framework for the high level synthesis of memory-intensive applications
TLDR
This paper presents bambu, a modular framework for research on high-level synthesis currently under development at Politecnico di Milano. Expand
  • 78
  • 9
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems
TLDR
We propose an ant colony optimization heuristic that, given a model of the target architecture and the application, efficiently executes both scheduling and mapping to optimize the application performance. Expand
  • 126
  • 6
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Implicit test generation for behavioral VHDL models
TLDR
This paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions based on the comparison between the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. Expand
  • 98
  • 6
A layout-similarity-based approach for detecting phishing pages
TLDR
In this paper, we present an extension of our system (called DOMAntiPhish) that mitigates the shortcomings of our previous system. Expand
  • 115
  • 4
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Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications
TLDR
This paper presents an innovative error model for algorithmic (behavioral) descriptions, which allows for the generation of behavioral test patterns that are used to perform the exploration of design alternatives based on testability. Expand
  • 30
  • 4
A Framework for the Functional Verification of SystemC Models
TLDR
The problems of error simulation, error model evaluation, and test generation are faced considering the peculiar features of this emerging system level design language to obtain a coherent, environment for functional verification. Expand
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Dynamic Reconfiguration: Core Relocation via Partial Bitstreams Filtering with Minimal Overhead
TLDR
This paper describes the development of a bitstream relocation filter, BiRF, that allows the relocation of a partial bitstream with minimal overhead during the download process. Expand
  • 37
  • 2
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis
TLDR
This paper presents a methodology for design space exploration (DSE) in high-level synthesis (HLS), based on a multi-objective genetic algorithm. Expand
  • 32
  • 2
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Functional test generation for behaviorally sequential models
TLDR
A test generation algorithm targeting a new coverage metric (called bit-coverage) that provides full statement coverage, branch coverage, condition coverage and partial path coverage for behaviorally sequential models. Expand
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  • 2
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