Fabrice Seguin

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The aim of this paper is to show the possibility to harvest RF energy to supply wireless sensor networks in an outdoor environment. In those conditions, the number of existing RF bands is unpredictable. The RF circuit has to harvest all the potential RF energy present and cannot be designed for a single RF tone. In this paper, the designed RF harvester adds(More)
An All-Fiber/sup /spl reg// tunable Mach-Zehnder delay line interferometer was developed for differential phase shift keying (DPSK) demodulation. Low loss and high isolation are maintained in a compact package by annealing the fibers at high temperature to relieve bending stresses. Reliability data is presented.
Based on multiple-slice turbo codes, a novel semi-iterative analog turbo decoding algorithm and its corresponding decoder architecture are presented. This work paves the way for integrating flexible analog decoders dealing with frame lengths over thousands of bits. The algorithm benefits from a partially continuous exchange of extrinsic information to(More)
Associative memories are data structures that allow retrieval of previously stored messages given part of their content. They thus behave similarly to human brain’s memory that is capable for instance of retrieving the end of a song given its beginning. Among different families of associative memories, sparse ones are known to provide the best efficiency(More)
Encoded neural networks mix the principles of associative memories and error-correcting decoders. Their storage capacity has been shown to be much larger than Hopfield Neural Networks'. This paper introduces an analog implementation of this new type of network. The proposed circuit has been designed for the 1V supply ST CMOS 65nm process. It consumes 1165(More)
Encoded neural networks mix the principles of associative memories and error-correcting decoders. This paper introduces an analog implementation of this new type of network to manage the power distribution in Multiprocessor System-on-Chip (MPSoC). The proposed circuit has been designed for the 1V supply ST CMOS 65nm process, with a low complexity and low(More)
This paper presents the design of an analog turbo decoder for DVB-RCS-like applications using a slice architecture. The constituent decoders for different frame lengths are made up of duplicated elements chosen from a small set of reduced-size MAP decoders. This slicing technique enhances the design of the decoder in terms of simplicity, testability,(More)
Higher density of integration and lower power technologies are becoming more sensitive to soft errors caused by radiations. Not only memories and latches are being affected but also combinatorial circuits. Hardening by design techniques based on increasing the amount of charge representing the bit and redundancy techniques have been used over the years.(More)