Fabrice Monteiro

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In this paper, we present a new network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The proposed NoC is based on new error detection mechanisms suitable for dynamic NoCs, where the number and position of processor elements or faulty blocks vary during runtime. Indeed, we propose online detection of data packet and(More)
The problem of designing a fault-secure interface between a fault-tolerant RAM memory system and a transmission channel, both protected against errors using cyclic linear error detecting and/or correcting codes is considered. The main idea relies on using the RAM check bits to control the correct operation of the parallel cyclic code encoder, so that the(More)
In this paper we present a new efficient online routing error detection approach dedicated to fault tolerant routing algorithms for the 2-D mesh reconfigurable Network-on-Chip interconnections. The main contribution is to distinguish a routing error due to switching failure from an adaptative routing decision (bypassing a faulty area or reconfigurable(More)
Nowadays, reconfigurable and multiprocessor systems are becoming increasingly attractive for many applications. Such systems should be more and more dependable especially if errors occur on bits which change the circuit functionality (reconfiguration bits). In addition, mechatronic and automatically controlled systems often work in harsh environmental(More)
LDPC codes are currently the most promising coding technique to achieve the Shannon capacity, making them very popular in modern telecommuncation applications. Despite the attractivity stemming from their effectiveness, encoding and decoding LDPC codes is a rather complex task, due to the size and structure of the codes, especially when considering the ever(More)
This paper proposes a new parallel implementation scheme to increase the bit rate of a cyclic code decoder. The principle is based on the partition of the architecture into a syndrome calculation block and an error accumulation block, in order to eliminate the error "decision" function from the feedback loop in the cyclic code decoder. This approach allows(More)
Dependable architectures play an important role in many areas that impact our lives. Dependability is achieved by using a set of analysis and design techniques that increases the complexity and consequently the cost of systems. In this paper, to meet low cost requirement of IP cores, we propose a simple dependable stack processor architecture using a(More)