Fabiano Fontana

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In developing Vantis' first FPGA family from a clean slate, our goal was to focus initially on the mainstream market needs of 12-36K+ logic gate range with an architecture that was scalable to higher densities. It had to be a high-performance, re-programmable FPGA family using SRAM technology; with a mainstream look-up-table (LUT) based architecture. It had(More)
A discrete-time realization of first-order (shelving) and second-order equalization filters is developed, providing bandpass/bandstop magnitude-complementary transfer functions. The bandpass transfer function is turned into a complementary one, and vice versa, switching between two structures that share a common allpass section containing the state(More)
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