Fabian L. Cabrera

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—In this paper we present the design of a wireless power receiver fully integrated. The circuit was constrained to occupy a silicon area of 1.5 mm × 1.5 mm in a 0.18 µm RF-CMOS process. The main target was to optimize the part of the power transfer efficiency concerning only the receiver side. In that way, we optimized the quality factor of the integrated(More)
This paper presents the design of a power amplifier integrated in a CMOS 180 nm technology, which is intended to drive an inductive link operating at 990 MHz. A class-D topology is employed to avoid the use of inductors. A design methodology is proposed to find the optimal transistor width, solving the trade-off between the ON-resistance and gate(More)
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