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—This paper presents the implementation and evaluation of an application-specific instruction set for a customizable RISC-processor for very high throughput stereo image processing. Compared to the base processor the overall processing time is accelerated by a factor of over 130, while the processor silicon area requirement increases only by a factor of(More)
This paper introduces a new FPGA architecture optimized for Frequency Modulated Continuous Wave (FMCW) Synthetic Aperture Radar (SAR). The architecture implements a Global-Backprojection-Algorithm (GBP) which has been modified to be independent of platform velocity (start-stop-approximation). The design supports parallelism of dedicated GBP processing(More)
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