Fa Foster Dai

Learn More
—This paper presents a 12 GHz direct digital synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 m SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of(More)
—This paper describes a 9-bit 6.2-GHz low power quadrature direct digital synthesizer (DDS) implemented in a 0.18-m SiGe BiCMOS technology. With a 9-bit pipeline accu-mulator and two 8-bit sine-weighted current steering DACs, this DDS is capable of generating quadrature sinusoidal waveforms up to 3.15 GHz with a maximum clock frequency of 6.2 GHz. Packed(More)
—A multiple-input/multiple-output (MIMO) trans-ceiver RFIC compliant with IEEE 802.11a/b/g and Japan wireless LAN (WLAN) standards is presented. The transceiver has two complete radio paths integrated on the same chip. When two chips are used in tandem to form a four-path composite beam forming (CBF) system, 15 dB of link margin improvement is obtained. The(More)
A novel 12-bit Vernier ring time-to-digital converter (TDC) with 8ps of time resolution for digital-phase-locked-loop applications is presented. The TDC achieves a large detectable range of 32ns. The core of the TDC occupies 0.75 x 0.35 mm 2 in a 0.13um CMOS technology. The total power consumption for the entire TDC chip is only 7.5mW with a 1.5V power(More)
This paper presents a novel direct digital frequency synthesis (DDFS) ROM compression technique based on two properties of a sine function: (a) piecewise linear technique to approximate a sinusoid, and (b) variation in the slope of the sinusoid at different phase angles. In the proposed DDFS architecture the ROM stores a few of the sinusoidal values, and(More)
— this paper presents an 8.7-13.8 GHz transformer-coupled varactor-less quadrature current-controlled oscillator (QCCO) RFIC. It incorporates a transformer-coupled technique and tuned by varying the operation current through the primary and secondary windings. Fabricated in a 0.13 µm SiGe BiCMOS process, the prototype QCCO achieves a 45.3% wide tuning(More)
—This letter presents a novel quadrature voltage controlled oscillator (QVCO) implemented in a 47-GHz SiGe BiCMOS technology. The QVCO is a serially coupled VCO that utilizes SiGe heterojunction bipolar transistors for oscillation and metal oxide semiconductor field effect transistors for coupling. The SiGe BiCMOS QVCO prototype achieves about 14.6% tuning(More)
— This paper presents a BiCMOS frequency synthesizer covering frequency range from 500 MHz to 2175 MHz which is fully compatible with DVB-S application. The frequency synthesizer consists of monolithic VCOs, utilizing on-chip symmetric inductor, high speed CML divider built with high performance BJT, and can achieve-80 dBc/Hz,-100 dBc/Hz,-123 dBc/Hz phase(More)
—We propose replica techniques with statistical post processing to improve integral non-linearity (INL) and code distribution performance of time-to-digital converters (TDC). We consider three different types of TDC namely: vernier delay line, multi-resolution, and ring oscillator based. We show that using a replica delay line with additional digital(More)
—This paper presents a low power, high speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse DAC and seven 3-bit fine DACs, the core area of the DDS is 3 × 2.5mm 2. The maximum clock frequency was measured at 8.6GHz(More)