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A highly configurable cache architecture for embedded systems
Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. TheExpand
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Embedded system design - a unified hardware / software introduction
Preface. Introduction. Custom Single-Purpose Processors: Hardware. General-Purpose Processors: Software. Standard Single-Purpose Processors: Peripherals. Memory. Interfacing. Digital Camera Example.Expand
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Automatic tuning of two-level caches to embedded applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimizations. We present anExpand
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A highly configurable cache for low energy embedded systems
Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. TheExpand
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Platune: a tuning framework for system-on-a-chip platforms
  • T. Givargis, F. Vahid
  • Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 10 December 2002
System-on-a-chip (SOC) platform manufacturers are increasingly adding configurable features that provide power and performance flexibility in order to increase a platform's applicability. This paperExpand
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A Survey on Concepts, Applications, and Challenges in Cyber-Physical Systems
The Cyber-Physical System (CPS) is a term describing a broad range of complex, multi-disciplinary, physically-aware next generation engineered system that integrates embedded computing technologiesExpand
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System-level exploration for Pareto-optimal configurations in parameterized systems-on-a-chip
Provides a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurations. These configurations representExpand
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Dynamic hardware/software partitioning: a first approach
Partitioning an application among software running on a microprocessor and hardware co-processor in on-chip configurable logic has been shown to improve performance and energy consumption in embeddedExpand
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A self-tuning cache architecture for embedded systems
Memory accesses can account for about half of a microprocessor system's power consumption. Customizing a microprocessor cache's total size, line size and associativity to a particular program is wellExpand
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SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design
System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the newExpand
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