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A highly configurable cache architecture for embedded systems
This work introduces a novel cache architecture intended for embedded microprocessor platforms that can be configured by software to be direct-mapped, two-way, or four-way set associative, using a technique the authors call way concatenation, having very little size or performance overhead. Expand
Embedded system design - a unified hardware / software introduction
This paper presents a meta-modelling system that automates the very labor-intensive and therefore time-heavy and therefore expensive and expensive process engineering process, called a single-Purpose Processor, by simplifying the design process. Expand
A Survey on Concepts, Applications, and Challenges in Cyber-Physical Systems
An extensive set of technical challenges are enumerated and specific applications are used to elaborate and provide insight into each specific concept in the Cyber-Physical System. Expand
Automatic tuning of two-level caches to embedded applications
This work introduces the two-level cache tuner, or TCaT - a heuristic for searching the huge solution space of possible configurations and shows the integrity of the heuristic across multiple memory configurations and even in the presence of hardware/software partitioning. Expand
Platune: a tuning framework for system-on-a-chip platforms
  • T. Givargis, F. Vahid
  • Engineering, Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 10 December 2002
The power estimation techniques for processors, caches, memories, buses, and peripherals combined with the design space exploration algorithm deployed by Platune form a methodology for design-of tuning frameworks for parameterized SOC platforms in general. Expand
A highly configurable cache for low energy embedded systems
A study of 23 programs drawn from Powerstone, MediaBench, and Spec2000 benchmark suites shows that the configurable cache tuned to each program saved energy for every program compared to a conventional four-way set-associative cache as well as compared to an conventional direct-mapped cache, with an average savings of energy related to memory access. Expand
Dynamic hardware/software partitioning: a first approach
This work describes the system architecture and initial on-chip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic partitioning of real benchmarks, and shows speedups averaging 2.6 for five benchmarks taken from Powerstone, Netbench and the own benchmarks. Expand
System-level exploration for Pareto-optimal configurations in parameterized systems-on-a-chip
The approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies and has successfully incorporated into the parameterized SOC tuning environment (Platune) and applied it to a number of applications. Expand
A self-tuning cache architecture for embedded systems
This work introduces on-chip hardware implementing an efficient cache tuning heuristic that can automatically, transparently, and dynamically tune the cache to an executing program, completely transparently to the programmer. Expand
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design
The SpecSyn system-level design environment is presented, which supports the new specify-explore-refine (SER) design paradigm, and the new paradigm and environment are expected to lead to a more than ten times reduction in design time. Expand