• Publications
  • Influence
Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level
TLDR
We introduce a miss table (MT) based cache locking scheme at level-2 (L2) cache to further improve the timing predictability and system performance/power ratio. Expand
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A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores
  • F. Sibai
  • Computer Science
  • IEEE Transactions on Parallel and Distributed…
  • 1 February 2012
TLDR
This paper introduces the Spidergon-Donut (SD) on-chip interconnection network for interconnecting 1,000 cores in future MPSoCs and CMPs. Expand
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Conotoxin protein classification using pairwise comparison and amino acid composition: toxin-aam
TLDR
We introduce a novel method (Toxin-AAM) for conotoxin superfamily classification that incorporates evolutionary information using a powerful means of pairwise sequence comparison and amino acid composition knowledge. Expand
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Iris recognition using artificial neural networks
TLDR
This paper presents a simple methodology for preprocessing iris images and the design and training of a feedforward artificial neural network for iris recognition. Expand
  • 55
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V-Set Cache Design for LLC of Multi-core Processors
TLDR
We propose v-set cache design for LLC in multi-core microprocessors. Expand
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Impact of level-2 cache sharing on the performance and power requirements of homogeneous multicore embedded systems
TLDR
We investigate the impact of the CL2 organization type (shared Vs distributed) on the performance and power consumption of homogeneous multicore embedded systems. Expand
  • 10
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Resource Sharing in Networks-on-Chip of Large Many-core Embedded Systems
  • F. Sibai
  • Computer Science
  • International Conference on Parallel Processing…
  • 22 September 2009
TLDR
We explore 4 on-chip interconnection networks (OCINs) in 64-core systems with switches shared by cores in core clusters and estimate their worst case latencies with Peh and Dally's router delay model and published wire delays. Expand
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Parallelization and Performance Evaluation of an Edge Detection Algorithm on a Streaming Multi-Core Engine
TLDR
In the world of multi-core processors, the STI Cell Broadband Engine stands out as a heterogeneous 9-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). Expand
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Ear recognition with feed-forward artificial neural networks
TLDR
In this paper, we define a 7-element ear feature set and design a feed-forward artificial neural network to recognize a human ear. Expand
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The distance-to-mean broadcast method for vehicular wireless communication systems
TLDR
We present a new statistical wireless broadcast communication method called distance-to-mean. Expand
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