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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
TLDR
The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator and the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity.
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Behavioral modeling of switched-capacitor sigma-delta modulators
This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC)…
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Curvature compensated BiCMOS bandgap with 1 V supply voltage
TLDR
A bandgap circuit capable of generating a reference voltage of 0.54 V is presented, implemented in a submicron BiCMOS technology, and achieves 5 ppm / K of accuracy without requiring additional operational amplifiers or complex circuits.
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Data Converters
This book is the first graduate-level textbook presenting a comprehensive treatment of Data Converters. It provides comprehensive definition of the parameters used to specify data converters, and…
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A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator
TLDR
This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR because it uses a comparator, named time-domainComparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.
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Analog Design for CMOS VLSI Systems
Preface. 1: The MOS Transistor. 1.1. Electrical Conduction in Solids. 1.2. Fermi-Dirac Statistic. 1.3. Properties of Materials. 1.4. CMOS Technology. 1.5. MOS Threshold Voltage. 1.6. I-V…
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Modeling sigma-delta modulator non-idealities in SIMULINK(R)
TLDR
This paper presents a complete set of SIMULINK(R) models, which allow exhaustive behavioral simulations of any sigma-delta modulator to be performed and results demonstrate the validity of the models proposed.
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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
TLDR
The proposed SAR ADC achieves rapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input.
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A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications
The design and implementation of a fully integrated complementary metal-oxide-semiconductor (CMOS) sixth-order 2.4 Hz low-pass fitter (LPF) for medical applications is presented. For the…
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A 200mA 93% Peak Efficiency Single-Inductor Dual-Output DC-DC Buck Converter
TLDR
A single-inductor dual-output DC-DC buck converter is presented and measurement results demonstrate that a peak power efficiency as high as 93.3% can be achieved and the efficiency is always >62.5%.
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