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A SystemC-based framework for modeling and simulation of networked embedded systems
Next-generation networked embedded systems pose new challenges in the design and simulation domains. System design choices may affect the network behavior and network design choices may impact on theExpand
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Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs
Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of complex designs without incurring the state explosion problem typical of the more traditional FSMs.Expand
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SystemC Cosimulation and Emulation of Multiprocessor SoC Designs
SystemC is an open source C/C++ simulation environment that provides several class packages for specifying hardware blocks and communication channels. The design environment specifies softwareExpand
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Implicit test generation for behavioral VHDL models
This paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison between the implicit description of theExpand
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On the integration of model-driven design and dynamic assertion-based verification for embedded software
Model-driven design (MDD) aims at elevating design to a higher level of abstraction than that provided by third-generation programming languages. Concurrently, assertion-based verification (ABV)Expand
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SAGA: SystemC acceleration on GPU architectures
SystemC is a widespread language for HW/SW system simulation and design exploration, and thus a key development platform in embedded system design. However, the growing complexity of SoC designs isExpand
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Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications
Presents an analysis of the behavioral descriptions of embedded systems to generate behavioral test patterns that are used to perform the exploration of design alternatives based on testability. InExpand
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Towards Equivalence Checking Between TLM and RTL Models
The always increasing complexity of digital system is overcome in design flows based on transaction level modeling (TLM) by designing and verifying the system at different abstraction levels. TheExpand
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Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On behalf of the IEEE/ACM International Conference on Hardware/Software-Codesign and System Synthesis (CODES+ISSS) Technical Program Committee, we would like to welcome you to the 10th CODES+ISSS.Expand
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Functional test generation for behaviorally sequential models
Functional testing of HDL specifications is one of the most promising approaches for the verification of the functionalities of a design before synthesis. The contribution of this work is theExpand
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