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An Object-based Fault-Tolerant Distributed Shared Memory Middleware
TLDR
This paper describes the design, implementation and experimental evaluation of an object-based middleware component developed in order to extend with fault tolerance capabilities an existing object- based Distributed Shared Memory (DSM) system. Expand
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Speeding Up Resting State Networks Recognition via a Hardware Accelerator
TLDR
This paper presents a hardware acceleration on FPGA design of the Independent Component Analysis (ICA), a state-of-the-art statistical method for RSNs recognition, in order to accelerate the data analysis process. Expand
Enabling transparent hardware acceleration on Zynq SoC for scientific computing
TLDR
In a quest for making FPGA technology more accessible to the software community, Xilinx recently released PYNQ, a framework for Zynq that relies on Python and overlays to ease the integration of functionalities of the programmable logic into applications. Expand