Learn More
A two-stage drain current phenomenon in saturation region, named as I<inf>d</inf>-V<inf>d</inf> hump, has been investigated in high-voltage NMOS transistor. A parasitic BJT turn-on enhanced I<inf>d</inf>-V<inf>d</inf> hump model is proposed and characterized by using a two-dimensional device simulation. By optimizing channel/drift-region process conditions,(More)
The relations between human-body-model (HBM) electrostatic discharge (ESD) waveform and transmission line pulsing (TLP) I-V curve on low temperature poly-Si (LTPS) thin film transistor (TFT) have been investigated in this paper. By using ESD zapper and TLP system, the ESD waveforms and TLP I-V curves on the LPTS TFT devices under different device dimensions(More)
  • 1