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- F. Jiménez-Molinos, F. Gámiz, A. Palma, J. A. López-Villanueva
- 2002

The direct and assisted-by-trap elastic tunnel current in metal–oxide–semiconductor capacitors with ultrathin gate oxide ͑1.5–3.6 nm͒ has been studied. Bardeen's method has been adapted to obtain the assisted tunnel current, in addition to the direct tunnel current. The dependence of the assisted current on the trap distribution in energy has also been… (More)

A Coulomb scattering model for ultrathin silicon-on-insulator inversion layers has been developed. This model simultaneously takes into account ͑i͒ screening of charged centers by mobile carriers, ͑ii͒ the distribution of charged centers inside the structure, ͑iii͒ the actual electron distribution, ͑iv͒ the charged center correlation, and ͑v͒ the effect of… (More)

- F. Jiménez-Molinos, A. Palma, F. Gámiz, J. A. López-Villanueva
- 2001

A physical model for trap-assisted inelastic tunnel current through potential barriers in semiconductor structures has been developed. The model is based on the theory of multiphonon transitions between detrapped and trapped states and the only fitting parameters are those of the traps ͑energy level and concentration͒ and the Huang–Rhys factor. Therefore,… (More)

We have measured the transition process from the high to low resistivity states, i.e., the reset process of resistive switching based memristors based on Ni/HfO 2 /Si-n+ structures, and have also developed an analytical model for their electrical characteristics. When the characteristic curves are plotted in the current-voltage (I-V) domain a high… (More)

- F. Gámiz, P. Cartujo-Cassinello, J. B. Roldán, F. Jiménez-Molinos
- 2002

We show by simulation that electron mobility and velocity overshoot are greater when strained inversion layers are grown on SiGe-On-insulator substrates ͑strained Si/SiGe-OI͒ than when unstrained silicon-on-insulator ͑SOI͒ devices are employed. In addition, mobility in these strained inversion layers is only slightly degraded compared with strained bulk… (More)

Electron transport in ultrathin double-gate (DG) silicon-on-insulator (SOI) devices is studied as a function of the transverse electric field and the silicon layer thickness, with particular attention to the evaluation of stationary drift velocity and low-field mobility at room temperature. A one-electron Monte Carlo simulator has been used.

– We present an analytical model to describe static and transient trap-assisted inelastic tunneling of electrons through insulating energy barriers. The model was implemented in a device simulator in order to calculate the gate current in metal-oxide-semiconductor capacitors, the trap occupancy in the gate oxides and the charging and discharging… (More)

- F. Gámiz, P. Cartujo-Cassinello, F. Jiménez-Molinos, J. E. Carceller
- 2003

We study the influence of the image and exchange-correlation effects in double-gate silicon-on-insulator ͑DGSOI͒ devices, in the calculation of both charge distribution and electron mobility. The image and exchange correlation potentials produce a greater confinement of the carriers and, according to the uncertainty principle, a greater phonon scattering… (More)

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