F. J. Twaddle

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Line edge roughness (LER) in end-of-the-roadmap integrated circuit interconnects causes variability in their resistance R, capacitance C and hence also their RC delay. We present an analysis of LER-induced variability of resistance, capacitance and delay of short-range interconnects within standard cells at the 32, 22 and 18 nm technology nodes using both a(More)
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