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A 389MIPS application processor for 3G cellular phones is implemented in a 0.13/spl mu/m dual-V, process. This dual-issue superscalar CPU with DSP runs at 216MHz at 1.2V and provides a resume-standby mode with a quick recovery feature using data retention of memory. The leakage current is estimated to be 98/spl mu/A when the power supply is internally cut(More)
An embedded-processor core implemented in a 130nm CMOS process runs at 400MHz and achieves 720MIPS with a power of 250mW and 2.8GFLOPS. The processor employs a dual-issue seven-stage pipeline architecture while maintaining 1.8MIPS/MHz instruction efficiency of the previous five-stage processor. The processor is suitable for digital consumer appliances.
A preamplifier with 45 GHz bandwidth and 50.2 dB/spl Omega/ transimpedance gain, a limiting amplifier with 32 dB gain and 49 GHz bandwidth, and a 40 Gb/s 1:4 high-sensitivity demultiplexer (HS-DEMUX) combined with a decision circuit are for use in a 40 Gb/s optical receiver. The bandwidth in the preamplifier and the maximum gain at 40 GHz in the limiting(More)
An application processor for 3G cellular phones, using 0.18 /spl mu/m CMOS technology, includes a single CPU and DSP core with an on-chip 128 kB SRAM. It enables software-based 15 frames/s MPEG-4 encoding of QCIF Simple @L1 at 70 MHz and 140 mW. Standby current of the processor is <10 /spl mu/A in a partially powered standby mode using separate power lines.
A fully integrated 39.8 to 43Gb/s OC-768 16:1 MUX/DEMUX chipset is implemented in a 0.18/spl mu/m BiCMOS process. Full-rate operation is realized with an on-chip VCO, and the chipset dissipates 11.6W. The measured output jitter of the packaged MUX is 630fs, and the sensitivity of DEMUX is 31 mV/sub PP/ single-ended with a BER <10/sup -12/.
40 Gb/s analog IC chipset, an AGC amplifier, a full-wave rectifier and a decision circuit, for optical receivers were developed using SiGe HBT technology. The high performance SiGe HBT and optimized circuit configuration make possible an AGC amplifier with a 47.8 GHz bandwidth, a full-wave rectifier, and a decision circuit with 40 Gb/s operation.
BACKGROUND Carmine is a natural red pigment obtained from dried gravid female cochineal insects (Dactylopius coccus or Coccus cacti). There have been several reports of allergies to carmine, but the major allergens responsible have not been identified. OBJECTIVE To identify the major allergenic proteins in cochineal. METHODS Immunoblots of purified(More)
An ultrahigh-speed 1-Mb emitter-coupled logic (ECL)-CMOS SRAM with 550-ps clock-access time, 900-MHz operating frequency, and 12-/spl mu/m/sup 2/ memory cells has been developed using 0.2-/spl mu/m BiCMOS technology. Three key techniques for achieving the ultrahigh speed are a BiCMOS word decoder/driver with an nMOS level-shift circuit, a sense amplifier(More)
This paper describes power reduction circuit techniques in an ultra-high-speed emitter-coupled logic (ECL)-CMOS SRAM. Introduction of a 0.25-/spl mu/m MOS transistor allows a Y decoder and a bit-line driver to be composed of CMOS circuits, resulting in a power reduction of 34%. Moreover, a variable-impedance load has been proposed to reduce cycle time. A(More)