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SpiNNaker is a novel chip - based on the ARM processor - which is designed to support large scale spiking neural networks simulations. In this paper we describe some of the features that permit SpiNNaker chips to be connected together to form scalable massively-parallel systems. Our eventual goal is to be able to simulate neural networks consisting of(More)
The design and implementation of globally asynchronous locally synchronous systems-on-chip is a challenging activity. The large size and complexity of the systems require the use of computer-aided design (CAD) tools but, unfortunately, most tools do not work adequately with asynchronous circuits. This article describes the successful design and(More)
The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally(More)
Keywords: Fault tolerance Globally asynchronous locally synchronous Low power system Massively-parallel architecture Spiking neural networks System-on-chip a b s t r a c t SpiNNaker is a biologically-inspired massively-parallel computer designed to model up to a billion spiking neurons in real-time. A full-fledged implementation of a SpiNNaker system will(More)
The design of a new high-performance computing platform to model biological neural networks requires scalable, layered communications in both hardware and software. SpiNNaker's hardware is based upon Multi-Processor System-on-Chips (MPSoCs) with flexible, power-efficient, custom communication between processors and chips. The architecture scales from a(More)
  • E. Painkras
  • 2004
This paper presents a SystemC based high-level design methodology for the hardware design and implementation of the Rijndael Advanced Encryption Standard (AES) as a soft Intellectual Property (IP) core suitable for both FPGAs and ASICs. The Rijndael algorithm has been implemented with minimal design effort, to achieve low resource/area usage with optimal(More)
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