Etsuko Okushi

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Accelerating a genetic algorithm (GA) by implementing it in a reconfigurable field programmable gate array (FPGA) is described. The implemented GA features: random parent selection, which conserves selection circuitry; a steady-state memory model, which conserves chip area; survival of fitter child chromosomes over their less-fit parent chromosomes, which(More)
Entire systems embedded in a chip and consistingof a processor, memory, and system-specific peripheral hardwareare now commonly contained in commodity electronicdevices. Cost minimization of these systems is of paramounteconomic importance to manufactures of these devices. Byemploying a variable configuration processor in conjunctionwith a multi-precision(More)
The problem of synthesizing a minimum-cost logic network is formulated for a genetic algorithm (GA). When benchmarked against the a commercial logic synthesis tool, an odd parity circuit required 24 basic cells (BCs) versus 28 BCs for the design produced by the commercial system. A magnitude comparator required 20 BCs versus 21 BCs for the commercial(More)
In this paper we present a design methodology to address the allocation/scheduling problem of a given parallel application task precedence graph (TPG) to a multiprocessor architecture referred to as ASIP array system using SystemC simulation models. The basic rationale of the proposed method is to develop modeling constructs and library in SystemC to help(More)
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