Erwin Janssen

Learn More
—A mathematical framework, based on state-space modeling, for the description of limit cycles (LCs) of 1-bit sigma–delta modulators (SDMs) is presented. It is proved that periodicity in bit output pattern of the SDM implies a periodic orbit in state-space variables. While the state-space description is generally applicable for periodic inputs, the focus is(More)
—This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register (SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The sampling front-end consists of four in-terleaved T/Hs at 650 MS/s that are optimized for timing accuracy and(More)
  • 1