Erwin Janssen

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—A mathematical framework, based on state-space modeling, for the description of limit cycles (LCs) of 1-bit sigma–delta modulators (SDMs) is presented. It is proved that periodicity in bit output pattern of the SDM implies a periodic orbit in state-space variables. While the state-space description is generally applicable for periodic inputs, the focus is(More)
—This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register (SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The sampling front-end consists of four in-terleaved T/Hs at 650 MS/s that are optimized for timing accuracy and(More)
— In this paper we present the results obtained sofar in an ongoing design pilot study for high-level system design. In order to gain insight and experience, we develop a mobile multi-media terminal using A|RT Designer by Adelante Technologies (former Frontier Design) [1]. This multi-media terminal supports a 4.8 kbps CELP codec and an MP3 decoder, giving(More)
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