Erwin Janssen

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A mathematical framework, based on state-space modeling, for the description of limit cycles (LCs) of 1-bit sigma–delta modulators (SDMs) is presented. It is proved that periodicity in bit output pattern of the SDM implies a periodic orbit in state-space variables. While the state-space description is generally applicable for periodic inputs, the focus is(More)
This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register (SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The sampling front-end consists of four interleaved T/Hs at 650 MS/s that are optimized for timing accuracy and(More)
This paper presents a two-stage fully integrated 60 GHz differential Low Noise Amplifier implemented in a TSMC bulk CMOS 65 nm technology. Implementation of a voltage-voltage feedback enables the neutralization of the Miller capacitance and the achievement of flat gain with a deviation of ± 0.25 dB over the entire 6 GHz bandwidth. It features a(More)
The paper introduces the coding technique that is used by the Super Audio CD system for lossless compression of 64 times oversampled one-bit audio data. The technique has been coined "DST" (direct stream transfer). The individual steps in the encoding and decoding process are detailed. The performance of the lossless compression algorithm, as a function of(More)
3BAbstract — This paper presents two monolithic transformer structures exhibiting high self resonance frequencies(fSR). Effect of positive and negative coupling factor on self resonance frequency is investigated. The transformer turn ratio and structure is selected to improve design and ease layout of a high frequency LNA and VCO. Measurement results of a(More)