Erwan Raffin

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In this paper, we present a novel method for merging sets of computational patterns into a reconfigurable cell respecting design constraints and optimizing specific design aspects. Each cell can then be used in a run-time reconfigurable processor extension. Our method uses constraint programming to define the pattern merging problem and therefore can easily(More)
Software video decoders for mobile devices are now a reality thanks to recent advances in Systems-on-Chip (SoC). The challenge has now moved to designing energy efficient systems. In this paper, we propose a light Dynamic Voltage Frequency Scaling (DVFS)-enabled software adapted to the much varying processing load of High Efficiency Video Coding (HEVC)(More)
This paper presents a system for application scheduling, binding and routing for a run-time reconfigurable operator based multimedia architecture (ROMA). We use constraint programming to formalize our architecture model together with a specific application program. For this purpose we use an abstract representation of our architecture, which models(More)
The increasing prominence of video oriented services, such as video conferencing, streaming or sharing, over other Internet services has made video decoding a must-have feature for any consumer device. As a complex signal processing task, video decoding puts a high pressure on battery-driven devices since battery autonomy becomes a key performance indicator(More)
This article presents a new tool for automatic design of application-specific reconfigurable processor extensions based on UPaK (Abstract <b>U</b>nified <b>Pa</b>tterns Based Synthesis <b>K</b>ernel for Hardware and Software Systems). We introduce a complete design flow that identifies new instructions, selects specific instructions and schedules a(More)
In the context of mobile handheld devices, energy consumption is a primary concern and the process of video decoding is often among the most resource-intensive applications. Recent embedded processors are equipped with advanced features such as dynamic voltage frequency scaling (DVFS) in order to reduce their power consumption. These features can be used to(More)
Heterogeneous computing systems increase the performance of parallel computing in many domains of general purpose computing with CPU, GPU and other accelerators. With Hardware developments, the software developments like Compute Unified Device Architecture (CUDA) and Open Computing Language (OpenCL) try to offer a simple and visual framework for parallel(More)
Implementing image processing applications in embedded systems is a difficult challenge due to the drastic constraints in terms of cost, energy consumption and real time execution. Reconfigurable architectures are good candidates to take-up this challenge and especially when the architecture is able to support different word-lengths of pixel through(More)