Erulappan Sakthivel

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Wireless sensor networks are engaged in various data gathering applications. The major bottleneck in wireless data gathering systems is the finite energy of sensor nodes. By conserving the on board energy, the life span of wireless sensor network can be well extended. Data communication being the dominant energy consuming activity of wireless sensor(More)
As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these(More)
In biomedical applications, the awareness in chip architectures with high performance has extended a lot of attention in market and research. A remarkable problematic situation for biomedical engineers is to monitor and analyze heart diseases, which is considered as the main reason or Electrocardiography (ECG), which plays vital role in heart medicines.(More)
Network on-chip (NoC) is a novel structural design template, which can be defied for complicated system level on-chip design. NoC has a potential to limit and present the bus-based communication. In this paper, the crisis to discuss is Low power consumption in an Asynchronous Network on-chip (NoC) level communication. NoC is implemented using FPGA which has(More)
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